Nonvolatile memory devices are commonly mounted in portable apparatus such as cellular phones or digital cameras and the use of them has been spreading at a rapid pace. In recent years, in many occasions, audio data and image data are used. Accordingly, there has been a strong demand for nonvolatile memory devices which have larger capacities and are operable at higher speeds. Furthermore, in fields of nonvolatile memory devices for use with portable apparatus, a demand for lower electric power consumption has been increasing.
At present, a major nonvolatile memory device is a flash memory. The flash memory is configured to control electric charges accumulated on a floating gate to store data. It has been pointed out that since the flash memory has a structure for accumulating electric charges on the floating gate in a high electric field, there is a limitation on reduction of the size, and it is difficult to miniaturize the flash memory, which is required to achieve a larger capacity. In addition, in the flash memory, specified blocks must be erased all at once for rewriting. Because of such a property, the flash memory requires a very long time for rewriting and has a limitation on an increase in the speed.
As a nonvolatile memory device in next generation which has a potential to solve the above mentioned problems, there is a nonvolatile memory device which incorporates resistance variable elements for storing data according to switching of electric resistance. As nonvolatile memories using resistance variable elements proposed currently, there are a MRAM (magnetic RAM), PRAM (phase-change RAM), ReRAM (resistive RAM), etc.
Patent document 1 discloses an exemplary control method of the ReRAM element using an oxide of a perovskite structure. Now, the control method of the ReRAM element will be described with reference to the drawings.
FIGS. 12 to 14 are views showing the control method of the memory cell disclosed in Patent document 1. A memory cell 9 includes a resistance variable element 1 and a select transistor 2. One terminal of the resistance variable element 1 is electrically connected to one main terminal (drain or source) of the select transistor 2. The other main terminal (source or drain) of the select transistor 2 is electrically connected to a source line terminal 3 via a source line 6. The other terminal of the resistance variable element 1 is electrically connected to a bit line terminal 5 via a bit line 8. A gate of the select transistor 2 is electrically connected to a word line terminal 4 via a word line 7. In any of the cases where data is written (“1” is written), data is erased (“0” is written) and data is read, a high-level ON-voltage is applied to the word line terminal 4 of the selected memory cell, placing the select transistor 2 in an electrically conductive state.
FIG. 12 is a view showing a state of application of voltage pulses when a write operation occurs in the memory cell of Patent document 1. The source line 6 is set to 0V (electrically grounded), and a positive write pulse having a predetermined write voltage amplitude is applied to the bit line 8 to write desired data to the resistance variable element 1. In the case where multi-valued data is written to the resistance variable element 1, a voltage amplitude of a write pulse is set to a level according to the value of data to be written. For example, in the case where four-valued data is written to one resistance variable element 1, one voltage amplitude is selected from among specified four voltage amplitudes determined to respectively correspond to the values of the write data and a write operation is performed. As a write pulse width, a proper width according to the element is selected. That is, to switch the element 1 to a predetermined resistance state, one voltage amplitude level and one pulse width corresponding to the resistance state exist.
FIG. 13 is a view showing a state of application of voltage pulses when an erase operation occurs in the memory cell of Patent document 1. The bit line is set to 0V (electrically grounded) and a positive erase pulse having a predetermined erase voltage amplitude is applied to the source line. Upon the application of the erase pulse, the electric resistance of the resistance variable element 1 is caused to have a minimum value. Patent document 1 discloses that, upon application of the erase pulse to a specified source line with plural bit lines set to 0V, data are erased all at once from plural memory cells connected to the plural bit lines and to the source line.
FIG. 14 is a view showing a state of application of a voltage pulse during a read operation in the memory cell of Patent document 1. When reading data stored in the resistance variable element 1, the source line 6 is set to 0V (electrically grounded), and a predetermined read voltage is applied to the selected bit line 8 via a read circuit. Upon application of the read voltage, a comparator/determiner circuit compares a level of the bit line 8 to a reference level for reading, and stored data is read. Non-patent document 1 discloses a ReRAM element configured to transition between a high-resistance state and a low-resistance state by application of voltage pulses having the same polarity and different voltages and pulse widths. TMO (transition metal oxide) is used as a resistance variable material for the ReRAM element of Non-patent document 1. The ReRAM element can be switched to a high-resistance state or to a low-resistance state in response to the electric pulses with the same polarity. FIG. 15 is a view showing a voltage-current characteristic of the ReRAM element of Non-patent document 1. As shown in FIG. 15, in “SET” in which the element is switched from the high-resistance state to the low-resistance state, a more current than before flows when the element has been switched from the high-resistance state to the low-resistance state unless a set current compliance is used. In this case, the element would switch back from the low-resistance state to the high-resistance state unexpectedly (incorrect operation), or would be broken down due to an excess current. Therefore, it is necessary to use Set Current Compliance at a predetermined first current value. In “reset” in which the element is switched from the low-resistance state to the high-resistance state, a current of a second value which is not smaller than the first current value flows.
As should be understood from above, for the ReRAM element which is switchable to the high-resistance state or to the low-resistance state by application of the voltages with the same polarity, it is necessary to control a driver circuit for causing switching of the resistance state so that the first current value or the second current value is selectively used, according to the resistance state of the element.    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2004-185756    Non-patent document 1: Baek, J. G. et al., 2004, “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, 0-7803-8684-1/04/$20.00IEEE